With advance of electronic devices in recent years, request for reduction in size and weight of the circuit-boards consisting of a wiring board and related electronic arts, not to speak of demand for higher performance of electronic devices, has become more and more intense. Hitherto, the packaging technology has evolved from the system in which DIP or PGA packages were mounted on a wiring board having through-holes to the system in which QFP or BGA packages are mounted on a wiring board having connecting circuits on the surface. Such evolution is credited to the realization of high-density packaging owing to the reduced dead space of the wiring board and facilitation of miniaturization and higher performance of the packages themselves. However, there is no end to the progress of electronic devices, and compatibilization of the request for higher performance of electronic devices and the request for reduction in size and weight of circuit-boards is still a serious thesis.
As a solution to the above problem, attention is focused on the method in which the semiconductor chips are not packaged but directly mounted on a wiring board. This method is roughly divided into two patterns according to the way in which the semiconductor chips and wiring board are joined.
In one pattern of the method, there is used the technique of wire bonding which has been generally employed in the art of packaging. Another pattern of the method comprises bump bonding. The latter technique is generally called flip chip bonding. This method is expected to pervade in the future as this technique facilitates multi-pin assembly since the electrodes can be formed in the mode of area array, and also as this bonding has good electrical properties because of short signal path.
According to the ordinary flip chip bonding method, a semiconductor chip and a substrate are electrically connected by means of reflowing, making use of the solder bumps provided on the metallic terminals having wettability of the semiconductor chip and the metallic terminals having wettability disposed on the pairing substrate.
To date, several proposals have been made on the mass productivity-improving structures of the substrate for mounting such a semiconductor chip, but all these proposals have merits and demerits, and there still is the thesis that a structure with high mass productivity is yet to be established.